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Title:
パルス時間差符号化回路
Document Type and Number:
Japanese Patent JP4215579
Kind Code:
B2
Abstract:

To provide an efficient, economical and high precision pulse time difference encoding circuit as compared with a conventional one in which the circuitry can be simplified, complexy in production of hardware is solved and time difference between two pulse signals can be measured accurately.

The pulse time difference encoding circuit comprises a pulse circulation circuit having a series connection of 2n-1 NOT gates and one NOR gate where 2n-2 NOT gates excepting the final stage and the NOR gate are connected in ring, delay time is equalized in all NOT gates and delay time of the NOR gate is set two times as long as that of the NOT gate. When a second pulse signal is inputted and a measurement is outputted from a counter/encoder circuit, it is outputted from the counter/encoder circuit while being delayed by a predetermined time from input of the second pulse signal.

COPYRIGHT: (C)2005,JPO&NCIPI


Inventors:
Nobuyuki Watanabe
Toshio Ozawa
Application Number:
JP2003185675A
Publication Date:
January 28, 2009
Filing Date:
June 27, 2003
Export Citation:
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Assignee:
Shimada Rika Co., Ltd.
International Classes:
H03K3/03; H03M5/02
Domestic Patent References:
JP6284014A
JP3220814A
Attorney, Agent or Firm:
Makoto Hagiwara



 
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