To control pulse width and to obtain a pulse signal whose mark rate is special by controlling power voltage through the use of a logic circuit (C-MOS) where the threshold of an input part depends on power voltage.

An input signal is applied to an input terminal IN and is integrated in an integral circuit 1. The signal passes through C-MOS being a logic circuit element where the threshold of the input part depends on power voltage and through an AGC circuit 5, and an output pulse signal is obtained from an output terminal OUT. An average value detection part 2 detects the average value of the input signal and an average value conversion part 3 controls power voltage VCC. When pulse width is narrowed, the average value of a pulse drops and the average value rises when pulse width is widened. Since the threshold of the input part of C-MOS is 1/2 of power voltage VCL, power voltage VCC is controlled with the average value of the input pulse signal, the threshold is dropped or raised, pulse width is widened or narrowed and the output signal of desired pulse width is obtained.