PULSE WIDTH MODULATED SIGNAL GENERATING CIRCUIT

Title:

PULSE WIDTH MODULATED SIGNAL GENERATING CIRCUIT

Document Type and Number:

Japanese Patent JP3696386

Kind Code:

B2

Abstract:

PROBLEM TO BE SOLVED: To obtain a pulse width modulated signal generating circuit by constituting a clock signal generating circuit and a clock phase control circuit of a phase variation circuit comprising only digital circuits using a CMOS process.
SOLUTION: A clock signal generating circuit 4 is constituted of a main phase variation circuit 10 outputting total 256 main delay clock signals. A phase clock selector 5 is provided with 256 phase clock signals and a clock select signal for selecting two clock signals out of 256 phase clock signals as two phase variation clock signals. A logical operating circuit 6 receives a logical operation select signal and two phase variation clock signals and selects one of two logical operation results as a pulse width modulation control signal based on the logical operation select signal.

Inventors:

Hideo Nagano
Yoshihide Suga

Application Number:

JP31410297A

Publication Date:

September 14, 2005

Filing Date:

November 14, 1997

Export Citation:

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Assignee:

Renesas Technology Corp.

International Classes:

B41J2/44; H03K7/08; H03K19/096; H03L7/093; (IPC1-7): H03K7/08; B41J2/44; H03K19/096; H03L7/093

Domestic Patent References:

JP6188691A
JP2294155A
JP6122232A
JP63069314A
JP6204826A
JP6204825A
JP5218832A
JP200091907A
JP6204827A
JP5283993A
JP4192914A

Attorney, Agent or Firm:

Hiroaki Tazawa
Konobu Kato
Hideaki Tazawa
Hamada Hatsune

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