Title:
PULSE WIDTH MODULATION CIRCUIT
Document Type and Number:
Japanese Patent JPH0936714
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To output a PWM signal with a simple circuit configuration by separating a data pulse signal into selection signals A, B, generating a delay signal D through the processing of the signal A and a clock signal C and allowing logic gate section to process the signals B-D. SOLUTION: A data register stores a pulse width data signal (a) consisting of a gate selection signal (c) generated by a most significant bit and a delay selection signal (b) generated by remaining low-order bits. A delay signal generating section 12 allows n-sets of unit delay circuits to delay sequentially a reference clock signal (e) depending on a value of the signal (b) to output delay signals d0-dn. Furthermore, the generating section 12 processes the signals d, b and selects any of the signals (d) and a logic gate section 13 receives the signals (d), (e) and applies NAND processing to them by using a signal (c) and outputs a PWM data signal. Thus, the pulse width is smoothly adjusted to generate a pulse with a high density and then the circuit is simplified by omitting a counter and a comparator.
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Inventors:
HO HIYON KIMU
Application Number:
JP30051195A
Publication Date:
February 07, 1997
Filing Date:
October 26, 1995
Export Citation:
Assignee:
LG SEMICON CO LTD
International Classes:
H03K7/08; H03K5/04; (IPC1-7): H03K5/04
Domestic Patent References:
| JPH0326016A | 1991-02-04 | |||
| JPH06278320A | 1994-10-04 |
Attorney, Agent or Firm:
Masaki Yamakawa
Next Patent: DELAY CIRCUIT