To provide a PWM pulse generation circuit and a control system using the circuit.
The magnitude of a count output from an up-down counter 6 and a subtraction result obtained by subtracting a dead time value set to a second register 4 from a duty factor set to a first register 2 is compared by three digital comparators 14, 16, 18. A first output is set at an inactive level, when counting operation is made larger than the duty factor by the first comparator 14, when the up-down counter 6 is up-count operated by a logical circuit 19. The first output is set at an active level, when counting operation is made smaller than the subtraction result by the third comparator 18 in a down-count operation. A second output is set at the active level, when counting operation is made larger than an addition result by the second comparator 16 in an up-count operation. The second output is set at the inactive level, when counting operation is made smaller with respect to the duty by the first comparator 14 in the down-count operation.
YAMAZAKI TAKANAGA
TAKECHI KENJI
MIZUNO KENJI
