To realize a circuit for generating a PWM signal capable of obtaining arbitrary multiple resolution for a reference clock, or controlling rising and falling in an arbitrary timing.
This PWM circuit for generating a PWM signal upon receiving a reference clock and rising timing data and falling timing data is provided with a delay circuit 120 for generating multiple delay signals by delaying the reference clock, a delay value measuring circuit 130 for measuring the delay value of the delay signal, timing arithmetic circuits 140a and 140b for deciding a delay signal by referring to the delay value and the rising timing data/falling timing data, selecting circuits 150a and 150b for selecting any delay signal as a rising signal and a falling signal according to the decision, and a PWM arithmetic circuit 160 for generating a PWM signal according to the rising signal and the falling signal.
TAKAGI KOICHI
IZUMIYA KENJI
