量子回路の最適化 - AEON Queue Incorporated

Title:

量子回路の最適化

Document Type and Number:

Japanese Patent JP7439109

Kind Code:

B2

Abstract:

A system and method is provided for optimizing an input quantum circuit. An exemplary method includes searching a library of templates to find, by compiling abstract gate operations into a set of hardware-specific operations that manipulate qubit states, a template of quantum circuit gates that performs a predetermined function and that matches a set of quantum circuit gates in the input quantum circuit that performs the predetermined function; and replacing the set of quantum circuit gates in the input quantum circuit with the template of quantum circuit gates when the template of quantum circuit gates has a lower quantum cost than the set of quantum circuit gates based on estimated execution times. Moreover, the method is executed in a pipeline in combination with at least quantum circuit compilation.

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Inventors:

Vandiva Chaplin
Yun Sung Nam

Application Number:

JP2021542569A

Publication Date:

February 27, 2024

Filing Date:

February 21, 2020

Export Citation:

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Assignee:

AEON Queue Incorporated

International Classes:

G06N10/00

Foreign References:

US20060123363

Other References:

MASLOV, Dmitri ほか,Quantum circuit simplification using templates,Proceedings of the Design, Automation and Test in Europe Conference and Exhibition,IEEE,2005年03月07日

Attorney, Agent or Firm:

Kazuyoshi Hayashi
Tetsuo Shiba
Takuya Saito
Mitsuru Iwaike
Kazuhiro Kosuge

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