Title:
RACH受信装置
Document Type and Number:
Japanese Patent JP4493830
Kind Code:
B2
Abstract:
The present invention provides an RACH receiving apparatus in which the components can be constructed in a small scale. The RACH receiving apparatus performs a demodulation processing so as to divide it into two stages of a first demodulation processing for multiplying reception data of complex-modulated RACH by sign codes subjected to an arithmetic processing with long codes and phase rotations in a code register multiplying unit, and a second demodulation processing for adding multiplication results every chips and multiplying addition results by signature codes in a signature multiplying unit.
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Inventors:
Ichiro Imaizumi
Jun Watanabe
Jun Watanabe
Application Number:
JP2000322966A
Publication Date:
June 30, 2010
Filing Date:
October 23, 2000
Export Citation:
Assignee:
Hitachi Kokusai Electric Co., Ltd.
International Classes:
H04L27/38; H04B1/16; H04B1/707; H04B1/7093; H04B15/00; H04K1/00; H04L27/30; H04B
Domestic Patent References:
| JP2001136103A |
Foreign References:
| WO2000036761A1 |
Other References:
ERICSSON,New RACH preambles with low auto-correlation sidelobes and reduced detector complexity,TSGR1#3(99)205,1999年 3月22日
Ericsson,Modulation of RACH preamble for PAPR reduction,TSGR1#4(99)339,1999年 4月18日,URL,http://www.3gpp.org/ftp/tsg_ran/WG1_RL1/TSGR1_04/Docs/Zips/r1-99339.zip
Ericsson,Modulation of RACH preamble for PAPR reduction,TSGR1#4(99)339,1999年 4月18日,URL,http://www.3gpp.org/ftp/tsg_ran/WG1_RL1/TSGR1_04/Docs/Zips/r1-99339.zip
Attorney, Agent or Firm:
Nobuhiro Funatsu
Kiyotaka Sakamoto
Kiyotaka Sakamoto