RADIO FREQUENCY DEMODULATING CIRCUIT WITH ZERO CROSS COUNTER

Title:

RADIO FREQUENCY DEMODULATING CIRCUIT WITH ZERO CROSS COUNTER

Document Type and Number:

Japanese Patent JPS6336603

Kind Code:

A

Abstract:

A digital frequency demodulator circuit works on the principle of determining the number of zero crossings of a band-limited input signal in a given period of time, in corresponding prior art analog circuits. The circuit includes an analog-to-digital converter, three delay elements, two edge detectors, an up/down counter, two arcsin read-only memories, a 1/2 multiplier and a multiple adder.

Inventors:

HAINRIHI PUAIFUAA
RAINAA SHIYUBEAA

Application Number:

JP17747786A

Publication Date:

February 17, 1988

Filing Date:

July 28, 1986

Export Citation:

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Assignee:

ITT IND GMBH DEUTSCHE

International Classes:

H03K9/06; H03D3/00; (IPC1-7): H03D3/00; H03K9/06

Attorney, Agent or Firm:

Takehiko Suzue

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