Title:
RAM TEST DEVICE
Document Type and Number:
Japanese Patent JPH05225071
Kind Code:
A
Abstract:
PURPOSE: To perform a RAM test in a short time by means of inexpensive configuration of hardware.
CONSTITUTION: A microprocessor 1 reads the test data written in RAM 3 at the time of test and sends it to a register 11 of a RAM test circuit 4, transferring the same test data directly to a register 12. Output signals of registers 11 and 12 are compared by a comparison circuit 13, detecting the equality or inequality of the both. In the case of an inequality, a detection signal of the logic '1' is latched by a flip-flop 14 to be read out on a bus through a buffer 15. The microprocessor 1 tests the RAN 3 by fetching the detection signals on the bus.
Inventors:
KAMO YASUSHI
Application Number:
JP2825592A
Publication Date:
September 03, 1993
Filing Date:
February 14, 1992
Export Citation:
Assignee:
RICOH KK
International Classes:
G06F11/22; G06F12/16; (IPC1-7): G06F11/22; G06F12/16
Attorney, Agent or Firm:
Kenjiro Take (2 outside)