Title:
半導体記憶装置の読み出し回路
Document Type and Number:
Japanese Patent JP4088954
Kind Code:
B2
Abstract:
By first readout, the current input from a selected cell is converted by a preamplifier and a VCO into pulses of a frequency inversely proportionate to the current value, and the number of the pulses within a preset time interval is counted by a counter 5 so as to be stored in a readout value register. A selected cell is then written to one of two storage states, and second readout is then carried out. The storage state of the selected cell is verified by comparing a count value of the counter for the second readout, a count value for the first readout as stored in a readout value register and a reference value stored in a reference value register to one another. By the use of the VCO, the integrating capacitor for the current or the generation of a reference pulse may be eliminated.
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Inventors:
Noboru Sakimura
Honda Yuji
Naohiko Sugibayashi
Honda Yuji
Naohiko Sugibayashi
Application Number:
JP2002056810A
Publication Date:
May 21, 2008
Filing Date:
March 04, 2002
Export Citation:
Assignee:
NEC
International Classes:
G11C11/14; G11C11/15; G11C7/06; G11C11/16; G11C16/04; H01L21/8246; H01L27/105; H01L43/08
Domestic Patent References:
| JP2001325791A | ||||
| JP10224190A |
Foreign References:
| WO2001024185A1 |
Attorney, Agent or Firm:
Yusuke Omi