Title:
READ ONLY MEMORY OF AMORPHOUS SILICON BASED NAND STRUCTURE AND MANUFACTURING METHOD THEREFOR
Document Type and Number:
Japanese Patent JP3008185
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a ROM device in which a source/drain region is insulated from a substrate below the source/drain region by the SOI structure and no leak current flows therebetween.
SOLUTION: A source/drain region 50 is insulated from a semiconductor substrate 30 below the source/drain region 50 by an SOI structure, to thereby prevent leak current from bowing therebetween. Failures caused by a diode junction between the semiconductor substrate 30 and the source/drain region 50 is prevented, to thereby improve the operating voltage. The source/drain region 50 of a MOSFET memory cell is formed out of intrinsic amorphous silicon instead of heavily-doped polysilicon. The ROM device manufacturing method is thus quite simplified.
Inventors:
▲温▼ 榮茂
Application Number:
JP19130097A
Publication Date:
February 14, 2000
Filing Date:
July 16, 1997
Export Citation:
Assignee:
Unihua Electronics Co., Ltd.
International Classes:
G11C17/00; H01L21/8246; H01L21/84; H01L27/112; (IPC1-7): H01L21/8246; H01L27/112
Domestic Patent References:
| JP4294582A | ||||
| JP536941A |
Other References:
【文献】米国特許5510287(US,A)
Attorney, Agent or Firm:
Eiji Saegusa (10 others)