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Patent Searching and Data


Title:
READ-ONLY MEMORY DEVICE
Document Type and Number:
Japanese Patent JPS6417462
Kind Code:
A
Abstract:

PURPOSE: To record information and to highly integrate a read-only memory device by interposing an insulating layer between the drain region and a bit line of a vertical MOS transistor.

CONSTITUTION: A MOS transistor for forming a memory cell is formed of a source region 5 formed in the bottom of a groove 3, and a drain region 8 formed on the top of a columnar bump 2, and a channel is vertically formed on the side face of the bump 2. Transistors of respective columns are formed integrally with its gate electrodes made of polycrystalline silicon and electrically connected to become word lines. The transistors are connected or not connected at its drain region 8 to a bit line 1 in response to the content of information.


Inventors:
HIRAYAMA TERUMINE
Application Number:
JP17352887A
Publication Date:
January 20, 1989
Filing Date:
July 11, 1987
Export Citation:
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Assignee:
SONY CORP
International Classes:
H01L27/112; G11C17/00; G11C17/12; H01L21/8246; H01L27/10; (IPC1-7): G11C17/00; H01L27/10
Attorney, Agent or Firm:
Hideaki Ogawa