PURPOSE: To shorten the whole of the read-out time by simultaneously giving addresses to all ROM elements and successively giving a timing signal to respective ROM elements to successively read out respective elements.

CONSTITUTION: When an address A is supplied from an address line and a control signal C is given from a control line, an address enable signal E is generated from an address decoder 3 and the address enable signal E is supplied to ROM elements 1 and 2 together with the address A. When a signal V1 goes to the low level after an access time TA elapses, data is read out twice continuously. In the first n-number of read-out operations, data in an area starting with the address A of the ROM element 1 is read by a timing signal T1 and data outputted from the ROM element 1 is selected by a selector 5 in accordance with a switching signal SX and is sent out to a data line. After the first n-number of read-out operations, a timing signal generator 4 stops generation of the timing signal T1 and starts generation of a timing signal T2 instead of the signal T1. Thus, the read-out time is shortened.