READ PREFERENTIAL MEMORY SYSTEM

Japanese Patent JP3757757

B2

PROBLEM TO BE SOLVED: To solve the problems that a wiring form for shortening write data processing time is taken conventionally though there are lot more memory accesses for read than the ones for write in an information processor, and since read/write timings are same, a delay adjustment circuit is put inside a DRAM as well and a cost increases. SOLUTION: Wiring is performed so as to give read accesses priority and read data are transferred. By adding a delay amount corresponding to propagation delay time to and from a module for the respective modules to write data, the stipulated time relation of a clock and the data is kept and the data are written. One-to-one wiring is provided so as to measure go and return reflection and reflected waves are measured to the reception time by a hysterisis receiver from the output time by the driver of the same impedance as wiring impedance.