PURPOSE: To control the read and the write of a peripheral device, which is operated in a low speed, without damaging the operation of a high-speed operation processing, by providing a control signal generating circuit in the output side of a gate circuit of the data read/write controlling system.

CONSTITUTION: When a CPU1 is operated by a clock signal (a) to take in data of a memory 5, a continuous address signal (b) of the memory 5 is outputted to an address bus 6, and a peripheral device controlling signal (f) is outputted to a gate circuit 4. The address signal (b) is decoded by a decoder 3 to which the output of the bus 6 is inputted, and a signal (c) is outputted for the time of two clock signals and is applied to the circuit 4 and the memory 5. A readout control signal (d) is outputted as the output of the circuit 4 and is applied to a control signal generating circuit 8, and the leading edge of the control signal (d) is detected by the circuit 8 to apply a single control signal (e) to the memory 5. Thus, the read and the write of a peripheral device which is operated in a low speed are controlled without damaging the high-speed processing operation.