RECEPTACLE FOR ELECTRONIC CIRCUIT PACKAGE LAMINATING LAYER

Title:

RECEPTACLE FOR ELECTRONIC CIRCUIT PACKAGE LAMINATING LAYER

Document Type and Number:

Japanese Patent JPS5665472

Kind Code:

A

Abstract:

A receptacle for stacked support of electronic packages provides ready address/selection of each package by disposing vertically spaced receptacle contact sets in offset relation longitudinally of an elongate package-receiving channel. Package stacking is facilitated by a fixed support for a lower package and a further support selectively movable into the package-receiving channel for supporting an upper package. Zero insertion force is provided by an actuator operable to displace receptacle contact sets from noninterfering disposition with respect to the channel into engagement with package contacts.

Inventors:

CHIYAARUZU JIEE DONAA
GOODON DEII KURISUTENSEN

Application Number:

JP14454480A

Publication Date:

June 03, 1981

Filing Date:

October 17, 1980

Export Citation:

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Assignee:

THOMAS & BETTS CORP

International Classes:

H01R12/71; H01R24/00; H01R33/76; H05K7/10; H01R13/193; (IPC1-7): H01R23/02; H01R33/76

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