PURPOSE: To changeover a reception re-timing of an S interface transceiver in matching with a transmission form.

CONSTITUTION: A transceiver is provided with a jitter quantity detector 10 detecting a jitter quantity of a clock signal 5 generated by a digital PLL circuit 4 and outputting a selector switching signal 6 when the detected jitter quantity is more than a predetermined threshold level. A retiming clock selection selector 7 for the transceiver selects a transmission clock signal 8 independently of a phase of reception data 1 when the selector 7 receives the selector switching signal 6 and selects the clock signal 5 when the selector 7 does not receive the selector switching signal 6 and inputs the selected signal to a reception retiming circuit 3 as a retiming clock signal 9.