Title:
位相ロックループのための再構成可能なＮ分周周波数生成
Document Type and Number:
Japanese Patent JP6663931
Kind Code:
B2
Abstract:
In an example, a phase-locked loop (PLL) circuit includes an error detector operable to generate an error signal; an oscillator operable to provide an output signal having an output frequency based on the error signal and a frequency band select signal, the output frequency being a frequency multiplier times a reference frequency; a frequency divider operable to divide the output frequency of the output signal to generate a feedback signal based on a divider control signal; a sigma-delta modulator (SDM) operable to generate the divider control signal based on inputs indicative of an integer value and a fractional value of the frequency multiplier, the SDM responsive to an order select signal operable to select an order of the SDM; and a state machine operable to, in an acquisition state, generate the frequency band select signal and set the order of the SDM.
Inventors:
Upadaya, Parag
Bekele, Adeba Bay M
Tarker Melek, Didem Jie
Woo, Jaoin Di
Bekele, Adeba Bay M
Tarker Melek, Didem Jie
Woo, Jaoin Di
Application Number:
JP2017556968A
Publication Date:
March 13, 2020
Filing Date:
April 26, 2016
Export Citation:
Assignee:
XILINX INCORPORATED
International Classes:
H03L7/197; H03K23/66; H03L7/089
Domestic Patent References:
| JP2006041580A | ||||
| JP2002026727A | ||||
| JP2010239554A | ||||
| JP2000341111A | ||||
| JP2002164786A | ||||
| JP2007300486A | ||||
| JP20139516A |
Attorney, Agent or Firm:
Fukami patent office