PURPOSE: To prevent the production of abnormal reproducing sound, by inhibiting the data latch when each bit of the PCM reproducing data for one sample period's share is all at high or low level.
CONSTITUTION: The parallel PCM signal every one sampling period in which the synchronizing pulse is inserted and which is recorded in the VTR9, is reproduced in the VTR9 and is separated into the PCM data and the synchronizing pulse at the signal separation circuit 11. The PCM data in this one sampling period is fed to the data failure detection circuit 22 in which the output is inverted when each bit of the PCM data in one sampling period is all at high or low level and the error detection circuit 15' discriminating CRC, and the synchronizing pulse is fed to the synchronizing failure detection circuit 23. The failure detection signals in the circuits 22 and 15' open the AND circuit 26 via the AND circuit 25 which is opened when the result of detection of the circuit 23 is normal, and the inhibit signal is fed to the latch circuit 24 to inhibit the latch to the circuit 24 at the PCM data failure in one sampling period in parallel conversion. Accordingly, no abnormal sound is produced in the reproduced sound in D/A conversion.
KUMAOKA MICHIAKI
FUKUMOTO NOBUO
