Title:
不揮発性メモリ・システムにおけるマルチページ障害の回復
Document Type and Number:
Japanese Patent JP6855102
Kind Code:
B2
Abstract:
A data storage system includes a controller and a non-volatile memory array having a plurality of blocks each including a plurality of physical pages. The controller maintains a logical-to-physical translation (LPT) data structure that maps logical addresses to physical addresses and implements a first data protection scheme that stripes write data over the plurality of physical blocks. In response to a read request requesting data from a target page stripe, the controller detecting errors in multiple physical pages of the target page stripe. In responsive to detecting errors in multiple physical pages of the target page stripe, the controller scans the LPT data structure to identify a set of logical addresses mapped to the target page stripe and triggers recovery of the target page stripe by a higher level controller that implements a second data protection scheme, wherein triggering recovery includes transmitting the set of logical addresses to the higher level controller.
Inventors:
Pretzka, Roman
Camp, Charles, John
Fly, aaron, daniel
Fisher, Timothy, John
Ioannou, Nicholas
Tomic, Sasa
Parnell, Thomas
Camp, Charles, John
Fly, aaron, daniel
Fisher, Timothy, John
Ioannou, Nicholas
Tomic, Sasa
Parnell, Thomas
Application Number:
JP2018527935A
Publication Date:
April 07, 2021
Filing Date:
December 09, 2016
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION
International Classes:
G06F11/10; G06F3/06; G06F3/08
Domestic Patent References:
| JP2015535120A | ||||
| JP2013539133A |
Foreign References:
| US20130042053 |
Attorney, Agent or Firm:
Takeshi Ueno
Tasaichi Tanae
Tasaichi Tanae