PURPOSE: To reduce the power consumption during a normal read operation(write operation) without modifying the number of refresh cycles by making the proportion of the memory cell blocks which is excited at the normal read operation(write operation) and refresh operation changeable.

CONSTITUTION: In normal read or write operation, a memory cell array 11 or 12 which contains the necessary data is selected in accordance with an address signal inputted from an external address input circuit 53. In the refresh mode, a refresh signal generating circuit 50 detecting the refresh mode by means of a signal from a CAS before RAS and exclusive refresh terminal, generates a refresh signal. The signal and an address signal from a refresh address counter circuit 52 are supplied to law decoders 21 and 22 through a memory cell block switching circuit 51, and all of the memory cell arrays 11 and 12 and sense amp. groups 41 and 42 are excited, and the refresh operation is executed.