PURPOSE: To reduce the number of times of refreshing without deteriorating the availability of an MPU by performing the next refresh during the idle time of the MPU after a constant time elapses at every time of the completion of the refresh.

CONSTITUTION: When the access of a dynamic (D) RAM6, a ROM7 by the MPU1 is completed, the MPU1 has the idle time and a refresh timing signal 16 from an oscillator 9 goes to H, a refresh permission signal from a refresh permission device 8 goes to H and a bus changeover device 5 is switched to a counter 2. A DRAM6 is refreshed by an address from the counter 2. After the refresh is completed, the signal 16 remains L for a constant time as it is, it is reversed to H in the idle time of the MPU1 after the constant time is elapsed, the next refresh is carried out and the refresh is not carried out at every idle time of the MPU1. Thereby, the number of times of the refreshing can be reduced without deteriorating the availability of the MPU and the consumption of power is reduced.