Title:
レギュレータ回路及びその制御方法
Document Type and Number:
Japanese Patent JP5408900
Kind Code:
B2
Abstract:
A regulator circuit for reducing the output noise when regulators are switched includes a linear regulator and a switching regulator. The linear regulator generates a first regulator voltage from an input voltage with a first feedback loop. The switching regulator generates a second regulator voltage from the input voltage with a second feedback loop, which is connected to the first feedback loop. A loop control circuit controls the first feedback loop so as to lower the first regulator voltage when the switching regulator is activated.
More Like This:
| JP2013165135 | SEMICONDUCTOR INTEGRATED CIRCUIT |
| JP2023090478 | SEMICONDUCTOR CIRCUIT AND POWER SUPPLY DEVICE |
| JP4892366 | Overcurrent protection circuit and voltage regulator |
Inventors:
Masami Aiura
Satoshi Takahashi
Satoshi Takahashi
Application Number:
JP2008118360A
Publication Date:
February 05, 2014
Filing Date:
April 30, 2008
Export Citation:
Assignee:
Freescale Semiconductor, Inc.
International Classes:
G05F1/56; H02M3/155
Domestic Patent References:
| JP2006204090A | ||||
| JP2005057919A | ||||
| JP2003525013A | ||||
| JP2003216247A |
Attorney, Agent or Firm:
Mamoru Kuwagaki