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Title:
RELAXATION OSCILLATOR WITH LOW POWER CONSUMPTION
Document Type and Number:
Japanese Patent JP2013128264
Kind Code:
A
Abstract:

To provide a relaxation oscillator which realizes increase in a frequency of the OSC_OUT signal without increasing current consumption.

A relaxation oscillator for generating an oscillator signal includes a ramp voltage generating circuit, a reference voltage generating circuit, a reference voltage switching circuit, and a digital logic circuit. The reference voltage generating circuit generates one or more reference voltages and the ramp voltage generating circuit generates one or more ramp voltages. The ramp voltages are compared with each of the reference voltages by sequential switching using a reference voltage switching signal generated by the reference voltage switching circuit. The oscillator signal generated by the digital logic circuit is based on the results of the comparisons.


Inventors:
SANJAY K WADHWA
DEEPENDRA K JAIN
Application Number:
JP2012000125197
Publication Date:
June 27, 2013
Filing Date:
May 31, 2012
Export Citation:
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Assignee:
FREESCALE SEMICONDUCTOR INC
International Classes:
H03K7/08; H03K4/06
Domestic Patent References:
JPH09312552A1997-12-02
JP2007243922A2007-09-20
JPH11298299A1999-10-29
JPH0469924U1992-06-22
JPH09312552A1997-12-02
JP2007243922A2007-09-20
JPH11298299A1999-10-29
Foreign References:
US6020792A2000-02-01
US6020792A2000-02-01
Attorney, Agent or Firm:
本田 淳