PURPOSE: To make it possible to utilize a bus efficiently at a high speed, by providing a time which operates while the use of the bus is permitted and a bus-use-end detecting circuit which receives its output signal and end signal and accepts a request to use the bus.

CONSTITUTION: Once supplied with a common-bus in-service signal from terminal 26 via inverter IV27, timer 24 counts up clock pulses from terminal 25 and sends its output to FF29 and selection terminal S0 of multiplexer MPX31 via IV28. An end signal from terminal 14 is supplied to selection terminal S1 and data terminals A2 and A3 of MPX31 via IV32. When instructions are finished normally, FF35 is set by the output of MPX31 on a rise in the end signal, thereby releasing the bus. On the other hand, when the end signal stays at "1" due to a fault, etc., FF35 is set by the clock right after the time of timer 24 is out and when the signal stays at "0", FF35 is set immediately after the time of timer 24 is out, thereby releasing the common bus. Consequently, the bus can be utilized with efficiency.