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Patent Searching and Data


Title:
REPETITIVE SIGNAL DETECTING CIRCUIT
Document Type and Number:
Japanese Patent JPS6337740
Kind Code:
A
Abstract:

PURPOSE: To preclude misdetection due to noise by deciding levels of the sent signals of a 1st and a 2nd filters.

CONSTITUTION: A demodulated signal is sent to a low-pass filter 1, also sent to a subtracter 2 to subtract its DC component, and sent to a delay device 3 and a multiplier 4. The delay device 3 delays the signal by one cycle and the multiplier 4 multiplies the sent output of the subtracter 2 by the conjugate signal of the sent signal of the delay device 3 and sends the result to a low-pass filter 5. The LPF 5 extracts the DC component of the sent signal of the multiplier 4 and sends it to a decision circuit 6, which generates a pulse only when the signal exceeds a predetermined threshold value. An absolute value circuit 7, on the other hand, calculates and sends the absolute value of the sent signal of the LPF 1 to a decision circuit 8, which generates a pulse only when the absolute value exceeds a predetermined threshold value. A discriminating circuit 9 generates a pulse indicating the arrival of a repetitive signal according to whether or not a pulse arrives. Consequently, the threshold values for the level indentification of the discriminating circuits 6 and 8 are set properly to preclude misdetection due to the noise.


Inventors:
HIRAGUCHI MASAYOSHI
Application Number:
JP18132786A
Publication Date:
February 18, 1988
Filing Date:
July 31, 1986
Export Citation:
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Assignee:
NEC CORP
International Classes:
H04L27/38; H04L27/00; (IPC1-7): H04L27/00
Attorney, Agent or Firm:
Uchihara Shin