To protect a semiconductor chip and bonding wires against damage caused by concentration of stress induced by a linear expansion coefficient difference between the semiconductor chip, the bonding wire, and a resin layer that covers them in a resin-sealed semiconductor device where a package base of cavity structure with a two-stepped recess is used.

A first resin layer 14 which is comparatively low in linear expansion coefficient and surrounds a semiconductor chip 12 and a second resin layer 14 which is comparatively high in linear expansion coefficient and covers bonding wires 13 are laminated inside a stepped recess 11 for resin sealing.