To miniaturize a memory cell and reduce manufacturing cost thereof.
A resistance change memory according to an embodiment includes a plurality of resistor change elements R arranged in a first direction with a first space SP1 therebetween and arranged in a second direction with a second space SP2 therebetween. A second conductive layer 14 constituting a first bit line is disposed on a side wall of a first insulation layer 13 and on a side wall of a first conductive layer 12, a width in the first direction is half or more of the first space SP1, and a width in the second direction is less than half of the second space SP2. A second insulation layer 15 is arranged on a side wall of the second conductive layer 14, and does not fill the second space SP2. A third conductive layer 16 constituting a second bit line fills the second space SP2.
Takakura Shigeo
Makoto Nakamura
Yoshihiro Fukuhara
Takashi Mine
Toshio Shirane
Nobuhisa Nogawa
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Morisezo Iseki
Takao Ako
Tadashi Inoue
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori