To reduce an area of a memory cell array.
A resistance change memory 10 includes a memory cell array 11 having a plurality of bit lines BL extending in a first direction, a plurality of word lines WL extending in a second direction, and a plurality of memory cells MC. Each memory cell MC includes a variable resistance element 21 and a selection transistor 22. A first terminal of the variable resistance element 21 is connected to a first bit line, a second terminal of the variable resistance element 21 is connected to a drain of the selection transistor 22, a source of the selection transistor 22 is connected to a second bit line, and a gate of the selection transistor 22 is connected to one of the word lines. In an layout of first to fourth variable resistance elements arranged in the first direction in this order, one word line is provided between the first and the second variable resistance elements, two word lines are provided between the second and the third variable resistance elements, and one word line is provided between the third and the fourth variable resistance elements.
SHIRATAKE SHINICHIRO
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Satoshi Kono
Makoto Nakamura
Yoshihiro Fukuhara
Takashi Mine
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Katsumura Hiro
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori
Takuzo Ichihara
Yamashita Gen
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