To present a layout which reduces cell area and improves operation characteristics excellently.
The resistance-change semiconductor memory has first through fourth memory cells arranged in the first direction. Each of the first through fourth memory cells includes cell transistors T11, T12, T13, T14 having first source/drain connected with a first bit line BLA1 extending in the first direction, and a gate connected with word lines WL1, WL2, WL3, Wl4 extending in the second direction, and resistive memory elements M11, M12, M13, M14 having one end connected with the second source/drain of the cell transistors T11, T12, T13, T14 and the other end connected with second bit lines BLB1, BLB2, BLB3, BLB4 extending in the second direction. First sources/drains in the first and second memory cells are shared, and first sources/drains in the third and fourth memory cells are shared.
Satoshi Kono
Makoto Nakamura
Yoshihiro Fukuhara
Takashi Mine
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Katsumura Hiro
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori
Takuzo Ichihara
Yamashita Gen