Title:
共振周波数タグ、および共振周波数タグの制御方法
Document Type and Number:
Japanese Patent JP4199801
Kind Code:
B2
Abstract:
A method of making a series of resonant frequency tags which each resonate at substantially the same predetermined frequency, the method comprising the steps of: (a) forming a series of first conductive patterns, the first conductive patterns all being substantially the same, each first conductive pattern comprising an inductive clement and a first land, the first land having a first end connected to one end of the inductive clement and a second end spaced a predetermined distance from the first end; (b) separately forming a series of second conductive patterns, the second conductive patterns all being substantially the same and each second conductive pattern comprising a second land and a link element, the second land having a predetermined width; (c) securing a second conductive pattern to a first conductive pattern of the series at a first predetermined location so that the second land overlies at least a portion of the first land with a dielectric therebetween to establish the plates of a capacitive element of a first tag of the series, the capacitive element having a first predetermined capacitance; (d) measuring the resonant frequency of the tag and comparing the measured frequency with the predetermined frequency; and (e) if the measured resonant frequency matches the predetermined frequency within a predetermined tolerance, securing a second conductive pattern to the subsequent first conductive pattern of the series at the first predetermined location so that the second land overlies at least a portion of the first land with a dielectric therebetween to establish the plates of a capacitive element of a subsequent tag, the capacitive element having the first predetermined capacitance and then repeating steps (d) and (e) for the remainder of the series and if the measured resonant frequency does not match the predetermined frequency within the predetermined tolerance, securing a second conductive pattern to a subsequent first conductive pattern of the series at a second predetermined location, different from the first predetermined location so that the second land overlies at least a portion of the first land with a dielectric therebetween to establish the plates of a capacitive element of a subsequent tag, the capacitive element having a second predetermined capacitance and then repeating steps (d) and (e) for the remainder of the series.
Inventors:
Eric Eckstine
Gary Mazoki
Peter Rendling
Luis Francisco Sorel Bonin
Go Matsumoto
Lawrence Apparucci
Gary Mazoki
Peter Rendling
Luis Francisco Sorel Bonin
Go Matsumoto
Lawrence Apparucci
Application Number:
JP2006508623A
Publication Date:
December 24, 2008
Filing Date:
January 23, 2004
Export Citation:
Assignee:
Checkpoint Systems, Incorporated
International Classes:
G06K19/07; G06K19/077; G08B13/24; H01F41/04; H03H1/00; H03H5/02; H01F5/00; H01F27/40
Domestic Patent References:
JP2001016022A | ||||
JP61036893A | ||||
JP2003044809A |
Foreign References:
WO2000079497A1 |
Attorney, Agent or Firm:
Takuji Yamada
Mitsuo Tanaka
Mitsuo Wada
Kazuhisa Inaba
Masahiro Ishino
Mitsuo Tanaka
Mitsuo Wada
Kazuhisa Inaba
Masahiro Ishino
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