PURPOSE: To eliminate the astable state of an output and to reduce design man-hours by constituting a flip-flop by using an inverting circuit, a logic circuit and an AND circuit so that a last output state is held when H-level signals are applied to 1st and 2nd input terminals after L-level signals are applied.

CONSTITUTION: The 1st input terminal S is connected to the 1st input terminal of a 1st OR circuit 7 and the 1st input terminal of a 4th OR circuit 10 through a 4th inverting circuit 6, and the 2nd input terminal is connected to the 1st input terminal of a 2nd OR circuit 8 through a 2nd inverting circuit 4 and to the 1st input terminal of a 3rd OR circuit 9. Further, the output terminals of the 1st and 2nd OR circuits are connected to the 1st input terminals of the 3rd and 4th OR circuits through a 1st AND circuit 11 and a 3rd inverting circuit 5, and the output terminals of the 3rd and 4th OR circuits and a 3rd input terminal CL are connected to the 2nd input terminals of the 1st and 2nd OR circuits through a 2nd AND circuit 12 and a 1st inverting circuit 3.