Title:
LADDER PROGRAM ANALYSIS DEVICE
Document Type and Number:
Japanese Patent JP2017207962
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a ladder program analysis device capable of giving information to improve execution efficiency of a ladder program.SOLUTION: A ladder program analysis device 100 comprises: a ladder program analysis unit 110; and a ladder program analysis result display unit 130. The ladder program analysis unit 110 analyzes a ladder program including a plurality of ladder circuits to create an execution order signal table 120 associating an execution order of the ladder circuits with a reference signal indicating a signal inputted into the ladder circuit and an update signal indicating a signal that the ladder circuit outputs. The ladder program analysis result display unit 130 compares the execution order of two ladder circuits with the reference signal and the update signal on the basis of the execution order signal table 120 to determine whether a ladder circuit execution efficiency of which can be improved exists or not and to display the determination result.SELECTED DRAWING: Figure 24
Inventors:
MATSUO TOSHIYUKI
MOCHIZUKI MITSURU
MOCHIZUKI MITSURU
Application Number:
JP2016100578A
Publication Date:
November 24, 2017
Filing Date:
May 19, 2016
Export Citation:
Assignee:
FANUC LTD
International Classes:
G05B19/05
Domestic Patent References:
| JP2007272679A | 2007-10-18 | |||
| JP3666507B2 | 2005-06-29 | |||
| JPH11110010A | 1999-04-23 | |||
| JPS61143809A | 1986-07-01 |
Attorney, Agent or Firm:
Aiwa Patent Business Corporation