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Patent Searching and Data


Title:
RUN LENGTH DECODER CIRCUIT
Document Type and Number:
Japanese Patent JPS6190571
Kind Code:
A
Abstract:

PURPOSE: To process a picture signal by word with use of a low-priced general- purpose microcomputer and to prevent the longer processing time with a simple circuit constitution by referring to a previously prepared bit/word conversion table and packing bits to a work register by word.

CONSTITUTION: Corresponding to a decoding request signal F from a reception control part, an MPU2 reads out a run length RL from a RAM1 at every word in the write order, identifies an identifying code by word and executes the bit to byte packing. At this time, the bit to byte packing is carried out by referring to a table stored in a ROM4 previously instead of a bit operation, in order to shorten a processing speed. The table includes three types S, X and Y which obey the relation between a run R denoted by a binary code of the run length RL and an idle bit B of a register 3 with respect to the immediately before word.


Inventors:
FUJITA KOJI
Application Number:
JP21211084A
Publication Date:
May 08, 1986
Filing Date:
October 09, 1984
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03M7/46; H04N1/419; (IPC1-7): H04N1/419
Domestic Patent References:
JPS5964969A1984-04-13
Attorney, Agent or Firm:
Uchihara Shin