PURPOSE: To execute satisfactory sampling-and-holding with simple configuration by executing the cascade connection of first and second CMOS switch elements and adjusting the phase of a sampling pulse to be supplied.

CONSTITUTION: The size of a CMOS switch element 5 is sufficiently enlarged and this element 5 is formed as an element having sufficiently low ON resistance. Then, the sizes of CMOS switch elements 2 and 4 are suppressed as prescribed exceeding limit, and these elements 2 and 4 are formed as elements having prescribed ON resistance. Further, the phase of a sampling pulse 2 to be supplied to the CMOS switch element 2 is slightly delayed for τ rather than the phase of a sampling pulse 1 to be supplied to the CMOS switch elements 2 and 4. Therefore in this circuit, since the size of the CMOS switch element 5 is sufficiently large so as not to generate the problem of dielectric strength and the sizes of the CMOS switch elements 2 and 4 are set as prescribed exceeding the limit, the gate capacity is reduced and the jump-in of the sampling pulse through this gate capacity is reduced.