Title:
スキャンフリップフロップ回路、スキャンテスト回路、半導体集積回路およびスキャンテスト方法
Document Type and Number:
Japanese Patent JP6449633
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a scan flip-flop circuit, a scan test circuit, a semiconductor integrated circuit, and a scan test method in which a reduction in operating speed or an increase in operating current during normal operation are suppressed.SOLUTION: A selection circuit SEL1 of a scan flip-flop circuit includes a circuit in which a series circuit in which an MP1 connected to a scan data input terminal si, an MP2 connected to the inverted terminal of a scan enable input terminal se, and an MP3 connected to a data input terminal d are connected in series and a series circuit in which an MP4 connected to the scan enable input terminal se and an MP5 connected to the inverted terminal of the scan enable input terminal se are connected in series are connected in parallel, the selection circuit SEL1 selecting and outputting either ordinary data or test data in accordance with the logic value of the scan enable input terminal se, the size of the MP2 being smaller than the sizes of other MOSFETs.SELECTED DRAWING: Figure 1
Inventors:
Kazuaki Goto
Application Number:
JP2014246252A
Publication Date:
January 09, 2019
Filing Date:
December 04, 2014
Export Citation:
Assignee:
LAPIS Semiconductor Co., Ltd.
International Classes:
H03K3/037; G01R31/28; H03K3/3562
Domestic Patent References:
| JP989988A | ||||
| JP10239400A |
Foreign References:
| US20130166978 |
Attorney, Agent or Firm:
Atsushi Nakajima
Kato Kazunori
Hiroshi Fukuda
Kato Kazunori
Hiroshi Fukuda
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