PURPOSE: To obtain uniform hysteresis characteristics, to decrease the number of elements, and to perform high-speed operation in case of integration, by setting the conductance ratio of an MOS transistor (TR) and a complementary MOS gate circuit according to a threshold voltage.

CONSTITUTION: Between an application point for a positive potential VDD and an earth potential point, a P-MOST31 and an N-MOST32 are connected in series. Then, both gates of the P-MOST31 and N-MOST32 are connected in common and an input signal IN is supplied to the common-connection point. Between the series connection point 33 of the P-MOST31 and N-MOST32 and VDD application point, a P-MOST34 is inserted and between the point 33 and earth, an N-MOST35 is inserted. The output of the circuit point 33 is led out as an output signal OUT through a C-MOS inverter 36 and also supplied to both the gates of the P-MOST34 and N-MOST35. To adjust a lower inversion threshold voltage, the conductance (gm) ratio of the P-MOST31 and N-MOST35 is set to a prescribed value, and to adjust a higher inversion threshold voltage, the (gm) ratio of the P-MOST34 and N-MOST32 is set to a prescribed value.