Title:
SCRAMBLER AND DESCRAMBLER
Document Type and Number:
Japanese Patent JP2003244132
Kind Code:
A
Abstract:
To provide a scrambler and a descrambler capable of bypassing data.
When bypassing, resistors 12-1 to 12-m are reset, all outputs of exclusive OR gates 10-2 to 10-m become low level and an incoming data is output from an exclusive OR gates 10-1 as it is. Consequently, a scrambler can confirm whether the data before scramble processing is correct or not. When bypassing, resistors 14-1 to 14-m are reset, all outputs of exclusive OR gates 16-2 to 16-m become low level and the data scrambled from an exclusive OR gate 16-1 is output as it is. Consequently, a descrambler can confirm what kinds of errors occurs from a transmission line to the descrambler.
Inventors:
ISHIWAKI MASAHIKO
Application Number:
JP2002040097A
Publication Date:
August 29, 2003
Filing Date:
February 18, 2002
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G09C1/00; H04L9/08; H04L9/22; H04L25/03; (IPC1-7): H04L9/22; G09C1/00; H04L9/08
Attorney, Agent or Firm:
Hisami Fukami (4 outside)