Title:
SELF-MODULATING TYPE CLOCK-GENERATING CIRCUIT
Document Type and Number:
Japanese Patent JP3613787
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce inter-cycle jitters in a clock generator, to which an EMI countermeasures are subjected.
SOLUTION: In a secondary PLL having a loop filter 7 constituted of a first capacity and a first resistance, the decrease in comparison frequencies can be suppressed by using a clock-modulating circuit 2 controlled by a signal 16 obtained by frequency-dividing the oscillation signal of a voltage-controlled oscillator 13 for recursively controlling a frequency-divider 15, and the generation of a high-frequency noise can be minimized, by using a primary ΔΣ modulator 21 to the clock-modulating circuit 2, and a system can be obtained as a third-order PLL, by using a second capacity 3 having a capacitative value which is not less than 1/10 times as large as that of the first capacity in parallel with the loop filter 7. Thus, inter-cycle jitters can be suppressed by effectively removing the high-frequency noise.
Inventors:
Satoru Miyabe
Application Number:
JP29566699A
Publication Date:
January 26, 2005
Filing Date:
October 18, 1999
Export Citation:
Assignee:
Japan Precision Circits Co., Ltd.
International Classes:
H03K4/94; G06F1/04; G06F1/08; H03K7/06; H03L7/183; H03L7/197; (IPC1-7): G06F1/04; G06F1/08; H03L7/183
Domestic Patent References:
| JP11220386A | ||||
| JP11195984A | ||||
| JP63164619A |
Foreign References:
| WO1992002080A1 |