Title:
SELF-RESETTING CMOS MULTIPLE CIRCUIT AND SIGNAL CONVERSION METHOD
Document Type and Number:
Japanese Patent JPH08111632
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To prevent an adverse effect based on time delay by including a data latch which has a true input and complementary input and output, responds to a 1st latch signal to take a 1st latch state and responds to a 2nd latch signal to take a 2nd latch state. SOLUTION: Four multiplexing circuits 202 to 208 have selection inputs A to D respectively. The circuits separately have true(t) outputs and complementary(c) outputs, too, and they are separately connected and form wired OR true outputs T and wired OR complement outputs C. The wired OR outputs are connected to a driver and latch circuit 210, and the circuit 210 generates a single static output. A reset circuit 212 is connected to (t) output and (c) output and starts the reset of each circuit 202 to 208 and the reset of the circuit 210 after a prescribed time period after either t output or c output is activated.
Inventors:
ANTOONIYO RATSUFUAERE PERETSUR
YUEN FUN CHIYAN
YUEN FUN CHIYAN
Application Number:
JP22872595A
Publication Date:
April 30, 1996
Filing Date:
September 06, 1995
Export Citation:
Assignee:
IBM
International Classes:
H03K3/356; H03K17/00; H03K17/693; H03K19/0948; G01R31/28; (IPC1-7): H03K3/356; G01R31/28; H03K17/00; H03K19/0948
Attorney, Agent or Firm:
Kiyoshi Goda (2 outside)