To reduce switching noise, to accelerate arithmetic speed and to improve accuracy by commonly connecting one terminal of a capacitor connected to each input terminal and inputting the commonly connected one terminal through an analog amplifier to a sense amplifier.

One terminal of a capacitor 2 is reset to the reset voltage of a reset power source 8 by a reset pulse RES. Next, when the reset pulse RES is turned off, both the terminals of the capacitor 2 are kept at respective reset potentials. When a transfer switch 3 is conducted by a transfer pulse T, a signal is transferred to one commonly connected terminal of the capacitor 2. The capacitor 2 connects one commonly connected terminal through an analog amplifier 12 to a sense amplifier 5. Therefore, when the voltage of an output terminal is inverted, an inverter 6 generates noise through its own gate capacitor to the input terminal but high-accuracy logical arithmetic can be executed without exerting any adverse influence upon the terminal voltage of the capacitor 2.