Title:
半導体装置、表示装置
Document Type and Number:
Japanese Patent JP5778638
Kind Code:
B2
Abstract:
In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.
Inventors:
Yoshimoto Kurokawa
Takayuki Ikeda
Teru Tamura
Uzumasa Munehiro
Masataka Ikeda
Ken Aoki
Takayuki Ikeda
Teru Tamura
Uzumasa Munehiro
Masataka Ikeda
Ken Aoki
Application Number:
JP2012171809A
Publication Date:
September 16, 2015
Filing Date:
August 02, 2012
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H04N5/374; H01L21/336; H01L27/146; H01L29/786; H04N5/357
Domestic Patent References:
| JP2010252118A | ||||
| JP2009540628A | ||||
| JP2009105381A | ||||
| JP2009535819A | ||||
| JP10285472A | ||||
| JP2002345797A |
Foreign References:
| WO2009119417A1 |