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Title:
SEMICONDUCTOR DEVICE OF HIGH WITHSTAND VOLTAGE
Document Type and Number:
Japanese Patent JPS5931061
Kind Code:
A
Abstract:

PURPOSE: To form a device in a structure suitable for high withstand voltage formation by a method wherein low impurity concentration regions are provided in the periphery of an impurity region which composes a transistor, resistor, etc., and wirings are provided on the low impurity concentration region.

CONSTITUTION: The base region of a N-P-N transistor, or the emitter and collector regions of a P-N-P transistor, and a resistor are composed by providing a P type diffused layer on the main surface of an N type semiconductor substrate 1. The regions 3 of low impurity concentration are formed in the periphery of this region 2. Then, the metallic wirings 5 are provided on the surface of the substrate 1 via an insulation film 4, without being positioned on the region 2, on the regions 3.


Inventors:
IMAIZUMI ICHIROU
KIMURA MASATOSHI
OCHI SHIKAYUKI
YOSHIMURA MASAYOSHI
YAMAGUCHI TAKASHI
KOUDA TOYOMASA
Application Number:
JP12325683A
Publication Date:
February 18, 1984
Filing Date:
July 08, 1983
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L27/04; H01L21/331; H01L21/822; H01L29/72; H01L29/73; (IPC1-7): H01L27/04
Attorney, Agent or Firm:
Katsuo Ogawa



 
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