Title:
SEMICONDUCTOR DEVICE IN CHIP-ON-CHIP STRUCTURE
Document Type and Number:
Japanese Patent JP3413120
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor device in a chip-on-chip structure for reducing a processing time.
SOLUTION: Surfaces of a main chip 1 and a sub-chip 2 are covered with a sealing film 26, and bumps BM and BS are provided in a projected state in a recessed part 27 of the sealing film 26. The main chip 1 and the sub-chip 2 are connected electrically by joining the bump BM and the bump BS directly. When the main chip 1 and the sub-chip 2 are joined, the sealing film 26 of the main chip 1 and the sealing film 26 of the sub-chip 2 are pressed to each other, so an inter-chip sealing layer 4 is formed and a space between the main chip 1 and the sub-chip 2 is sealed with the inter-chip sealing layer 4.
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Inventors:
Satoshi Nakamura
Application Number:
JP4521299A
Publication Date:
June 03, 2003
Filing Date:
February 23, 1999
Export Citation:
Assignee:
ROHM Co., Ltd.
International Classes:
H01L25/18; H01L21/60; H01L23/48; H01L23/52; H01L25/065; H01L25/07; H01L29/40; (IPC1-7): H01L25/065; H01L21/60; H01L25/07; H01L25/18
Domestic Patent References:
| JP63142663A | ||||
| JP63141356A | ||||
| JP39555A | ||||
| JP10335576A |
Attorney, Agent or Firm:
Inaoka Kozo (1 person outside)