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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE AND ITS FABRICATION PROCESS
Document Type and Number:
Japanese Patent JP2008182121
Kind Code:
A
Abstract:

To provide a semiconductor device in which ESD (Electro-Static Discharge) tolerance is enhanced by solving the problem wherein it is difficult to reduce a chip size because a diode used in a clamp circuit is formed in the epitaxial layer in the horizontal direction.

In the semiconductor device 1, an N-type buried diffusion layer 6 and a P-type buried diffusion layer 7 are formed while being superimposed across a substrate 2 and an epitaxial layer 3, and an N-type diffusion layer 9 is formed to be superimposed on the P-type buried diffusion layer 7. By this structure, a diode D1 having a PN junction region 15 and a diode D2 having a PN junction region 17 are formed in the depth direction (Y axis direction) of the epitaxial layer 3. The chip size is reduced by preventing spread of a bidirectional diode 1 in the horizontal direction (X axis direction).


Inventors:
OTAKE SEIJI
Application Number:
JP2007015462A
Publication Date:
August 07, 2008
Filing Date:
January 25, 2007
Export Citation:
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Assignee:
SANYO ELECTRIC CO
SANYO SEMICONDUCTOR CO LTD
International Classes:
H01L29/866; H01L21/822; H01L21/8234; H01L27/04; H01L27/06; H01L27/088
Domestic Patent References:
JP2003347560A2003-12-05
JPS5113010Y11976-04-07
JP2002198436A2002-07-12
Attorney, Agent or Firm:
Hiroshi Kakutani