To provide a semiconductor device in which ESD (Electro-Static Discharge) tolerance is enhanced by solving the problem wherein it is difficult to reduce a chip size because a diode used in a clamp circuit is formed in the epitaxial layer in the horizontal direction.
In the semiconductor device 1, an N-type buried diffusion layer 6 and a P-type buried diffusion layer 7 are formed while being superimposed across a substrate 2 and an epitaxial layer 3, and an N-type diffusion layer 9 is formed to be superimposed on the P-type buried diffusion layer 7. By this structure, a diode D1 having a PN junction region 15 and a diode D2 having a PN junction region 17 are formed in the depth direction (Y axis direction) of the epitaxial layer 3. The chip size is reduced by preventing spread of a bidirectional diode 1 in the horizontal direction (X axis direction).
SANYO SEMICONDUCTOR CO LTD
JP2003347560A | 2003-12-05 | |||
JPS5113010Y1 | 1976-04-07 | |||
JP2002198436A | 2002-07-12 |
Next Patent: REACTOR CORE AND REACTOR