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Title:
SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP2004214512
Kind Code:
A
Abstract:

To provide a semiconductor device which can reduce a layout area needed for connecting a storage node with a gate electrode to have the same potential as that of the storage node, and can achieve a high manufacturing yield because of its simple structure; and to provide its manufacturing method.

This semiconductor device comprises diffused layers 205a, 205b which are formed in a semiconductor substrate 201, the gate electrode 204 which is formed on the semiconductor substrate 201 through a gate insulating film 203, an interlayer insulating film 207 which is formed on the semiconductor substrate 201 covering the gate electrode 204, and a capacitor which is formed on the substrate 207 and has a laminated structure composed of a lower electrode 210, a dielectric film 211, and an upper electrode 212. The diffused layer 205b, gate electrode 204 and lower electrode 210 are connected by a common contact 208 which is formed in the interlayer insulating film 207.


Inventors:
AMOU ATSUSHI
HACHISUGA ATSUSHI
KASAOKA TATSUO
Application Number:
JP2003001501A
Publication Date:
July 29, 2004
Filing Date:
January 07, 2003
Export Citation:
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Assignee:
RENESAS TECH CORP
International Classes:
G11C15/04; G11C11/405; H01L21/768; H01L21/8242; H01L27/02; H01L27/108; (IPC1-7): H01L21/8242; G11C11/405; G11C15/04; H01L27/108
Domestic Patent References:
JP2001338991A2001-12-07
JP2002093924A2002-03-29
JP2001196564A2001-07-19
JPH11145468A1999-05-28
JP2002289702A2002-10-04
JP2001144192A2001-05-25
Attorney, Agent or Firm:
Mamoru Takada
Hideki Takahashi
Atsuko Oaku
Atsushi Hirayama
Tamaki Otsuka



 
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