Title:
半導体装置およびその作製方法
Document Type and Number:
Japanese Patent JP4583529
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a technique for manufacturing a crystalline TFT of a structure which a gate electrode and an LDD region are overlapped, by a simple method. SOLUTION: In an n-channel TFT, a structure in which an LDD region is overlapped with a gate electrode is formed. For this purpose, a process wherein the gate electrode is formed of a first conductive layer and a second conductive layer, an impurity element which gives a first n-type is added after the first conductive layer is formed, a first impurity region to be used as the LDD region is formed and an impurity element, which gives a second n-type is added after the second conductive layer is formed, is performed. A second impurity region, which is used as a source region and a drain, is formed. In this manner, a structure in which the LDD region is overlapped with the gate electrode is realized. In addition, in order to form the LDD region which does not overlap with the gate electrode, it is sufficient to remove a part of the second conductive layer.
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Inventors:
Shunpei Yamazaki
Hiroki Adachi
Hiroki Adachi
Application Number:
JP31771499A
Publication Date:
November 17, 2010
Filing Date:
November 09, 1999
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
G09F9/30; H01L21/336; G02F1/136; G02F1/1365; G02F1/1368; H01L27/32; H01L29/786
Domestic Patent References:
| JP8018055A | ||||
| JP10163498A | ||||
| JP1999039241A |