To provide a semiconductor device in which test time is reduced and testing cost is also reduced so as to attain cost reduction and to provide its test method.
A comparator 25 compares data read from each memory cell within a memory cell array 19 with expected values and normal/defective condition of the memory cell is determined by conducting program inspection and erase inspection. Based on the comparison result of the comparator, a detected defective cell is replaced and relieved by a spare cell. Information of the defective cell is stored in registers 62 and 63 every time a defective cell is replaced by a spare cell. Based on the information, presence and absence of a defective cell and propriety of the relief are determined. When relief is made possible, control by a control circuit 11 is executed, a detected defective cell is replaced and relieved by the spare cell. When it is impossible to make relief, relief of a defective cell is stopped.
HIRATA YOSHIHARU
KUZUNO NAOKAZU
TOSHIBA LSI SYSTEM SUPPORT KK
| JP2000057795A | 2000-02-25 | |||
| JPH04228196A | 1992-08-18 | |||
| JP2001043698A | 2001-02-16 | |||
| JP2002117699A | 2002-04-19 |
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Sadao Muramatsu
Ryo Hashimoto