Title:
SEMICONDUCTOR DEVICE AND ITS TESTING METHOD
Document Type and Number:
Japanese Patent JP3654013
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce development man-hours by generating a test pattern in a storage and writing it into a storage element, reading a group of data access signal lines, and reading the test pattern from a logic circuit device to an external terminal.
SOLUTION: In test operation, a row address selection circuit 108 and a column address selection circuit 109 select a test row address signal 126 and a test column address signal 128 and outputs a selective row address 117 and a selective column address 118, respectively. In synchronization with an incremented test column address, test write data 119 is outputted from a test circuit 110 with adjacent signal lines as opposite polarities. The data is simultaneously read after writing is completed, is taken into a shift FF array 122 from a group of signals 121 for accessing data, and then a shift control signal 123 is enabled, and the data stream being taken in is taken out of the shift output. As a result, the connection of the group of signals 121 for connecting the storage device 101 and the logic circuit device 111 can be verified and also the short-circuiting of the adjacent signal lines can be verified.
Inventors:
Nobuyuki Nakai
Application Number:
JP33242398A
Publication Date:
June 02, 2005
Filing Date:
November 24, 1998
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G11C11/401; G11C29/00; G01R31/28; G11C29/02; (IPC1-7): G01R31/28; G11C29/00
Domestic Patent References:
| JP8292235A | ||||
| JP6289099A | ||||
| JP643744A |
Attorney, Agent or Firm:
Fumio Iwahashi
Tomoyasu Sakaguchi
Hiroki Naito
Tomoyasu Sakaguchi
Hiroki Naito
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